I. Field of the Disclosure
The technology of the disclosure relates generally to memory systems employing addressable static memory bit cells for reading and writing data, and more particularly to read assist circuits for mitigating read disturb conditions when reading from bit cells.
II. Background
Supply voltage (i.e., Vdd) scaling is an effective technique for maximizing processor energy efficiency across all market segments, ranging from small, embedded cores in a system-on-a-chip (SoC) to large multicore servers. As supply voltage in processor-based systems is reduced to conserve power, circuit delay sensitivity to parameter variations amplifies, eventually resulting in circuit failures. These circuit failures limit the minimum operating supply voltage and the maximum energy efficiency of processor-based systems. In current processor-based system designs, static random-access memory (SRAM) caches and/or register files limit the minimum operation supply voltage. SRAM cache and register file bit cells employ near minimum-sized transistors to maximize capacity. Since uncorrelated parameter variations (e.g., random-dopant fluctuations, line-edge roughness) are inversely proportional to the square-root of the transistor gate area, wide differences exist for the memory bit cell minimum operating voltage to read, write, and retain data.
In this regard, FIG. 1 is a schematic diagram of an exemplary SRAM system 100 employing memory bit cells 102(0)(0)-102(M)(N) (“bit cells 102(0)(0)-102(M)(N)) for storing data in a data array 104. The data array 104 is organized as having ‘N+1’ bit cell columns and ‘M+1’ bit cell rows of bit cells 102 supporting an ‘N+1’ bit wide data word. A bit line driver 112(0)-112(N) is provided for each bit cell column 0-N to drive a selected bit line 114(0)-114(N) and a complement bit line (bit line_b) 114′(0)-114′(N) for read and write operations. A wordline driver 108(0)-108(M) is provided for each bit cell row 0-M in the data array 104 to control access to the addressed bit cells 102( )(0)-102( )(N) in a given bit cell row 0-M based on an index(0)-index(M) decoded from a memory address indicating the bit cell row 0-M to be selected. A clock signal (clk) 110 controls the timing of asserting the activated wordline 106(0)-106(M) to access a row of bit cells 102( )(0)-102( )(N) in the selected bit cell row 0-M. The wordline driver 108(0)-108(M) for the selected bit cell row 0-M causes the data stored in the selected bit cells 102( )(0)-102( )(N) to be asserted onto the bit lines 114(0)-114(N) and complement bit lines 114′(0)-114′(N) to be sensed by sense amplifiers 116(0)-116(N) provided in each bit cell column 0-N. The sense amplifiers 116(0)-116(N) provide the data bits from the selected bit cells 102( )(0)-102( )(N) onto respective data output lines 118(0)-118(N).
FIG. 2 is a circuit diagram of a bit cell 102 in the SRAM system 100 in FIG. 1. In this example, the bit cell 102 is a standard six (6) transistor (6-T) static complement memory bit cell. The bit cell 102 comprises two (2) cross-coupled inverters 120(0), 120(1) powered by voltage Vdd. The cross-coupled inverters 120(0), 120(1) reinforce each other to retain data in the form of a voltage on a respective true node (T) 122 and a complement node (C) 122′. Each inverter 120(0), 120(1) is comprised of a respective pull-up P-type Field-effect Transistor (PFET) 124(0), 124(1) coupled in series to a respective pull-down N-type Field-effect Transistor (NFET) 126(0), 126(1). NFET access transistors 128(0), 128(1) are coupled to the respective inverters 120(0), 120(1) to provide respective read/write ports 130(0), 130(1) to the bit cell 102. In a read operation, the bit line 114 and complement bit line 114′ are pre-charged to voltage Vdd. Then, the wordline 106 coupled to gates (G) of the NFET access transistors 128(0), 128(1) is asserted to evaluate the differential voltages on the true node 122 and complement node 122′ to read the bit cell 102. If a logic high voltage level (i.e., a ‘1’) is stored at the true node 122 (T=1) and a logic low voltage level (i.e., ‘0’) is stored at the complement node 122′ (C=0), assertion of the wordline 106 will cause the NFET access transistor 128(1) to discharge the pre-charged voltage on the complement bit line 114′ to the complement node 122′ and through the NFET 126(1) to ground. However, if the NFET access transistor 128(1) is a faster device than the PFET 124(1), the discharge of the pre-charged voltage on the complement bit line 114′ can cause a charge build up on complement node 122′ that can cause inverter 120(0) to flip the voltage on the true node 122 from a logic ‘1’ to a logic ‘0’, which may cause a subsequent read operation to the bit cell 102 to return erroneous data. This is known as a read disturb condition.
To mitigate or avoid a read disturb condition from occurring in the bit cell 102 in FIG. 2, the NFET access transistors 128(0), 128(1) could be weakened and the PFETs 124(0), 124(1) in the inverters 120(0), 120(1) be strengthened. However, this can cause write contention issues in the bit cell 102. FIG. 3 is a circuit diagram illustrating a write contention between the NFET access transistor 128(0) and the PFET 124(0) in the inverter 120(0) in the bit cell 102 in FIG. 2. For example, during a write operation, if a logic ‘1’ is stored in the true node 122 (T=1) (and a logic ‘0’ is stored in the complement node 122′ (C-0)) and the data placed on the bit line 114 to be written to the true node 122 is a logic ‘0’, the NFET access transistor 128(0) couples the true node 122 to the bit line 114 to write a logic ‘0’ to the true node 122. The NFET access transistor 128(0) is capable of passing a strong logic ‘0’. However, the logic ‘0’ stored in the complement node 122′ can cause the strengthened PFET 124(0) to overcome the drive strength of the NFET access transistor 128(0) to charge the true node 122 to voltage Vdd (i.e., a logic ‘1’), thus causing a write contention on the true node 122.